JOB: DDR RTL Design Engineer At Cadence

Location: Bengaluru and Noida

Firm: Cadence

Place Description:

  • RTL Design Engineer for DDR Reminiscence Controller IP improvement group.
  • The place is predicated in Bangalore.
  • The position would come with the design and assist of the RTL of the DDR Reminiscence Controller answer of Cadence. All main DDR reminiscence protocols will likely be supported – together with DDR4/LPDDR4.
  • The work concerned will likely be working with the present RTL, the addition of latest options into the RTL, making certain varied buyer configurations are clear as a part of verification regressions, supporting prospects, and making certain the design is clear for LINT and CDC design pointers.

Place Necessities:

  • BE/B.Tech/ME/M.Tech – Electrical / Electronics / VLSI with expertise as a design and verification engineer, with a big portion of the latest work expertise on RTL design and improvement.
  • RTL Design utilizing Verilog is a should.
  • System Verilog expertise and expertise with UVM-based atmosphere utilization / debugging are required.
  • AXI3/4 expertise is desired.
  • DDR Reminiscence controller and protocol expertise are extremely fascinating. Prior expertise in RTL design and implementation of complicated protocols is a should.
  • Prior expertise in IP improvement groups can be an added benefit.

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